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1/67 july 2002 m7010r 16k x 68-bit entry network search engine features summary 16k entries in 68-bit mode table may be partitioned into up to four (4) quadrants (data entry width in each quadrant is config- urable as 34, 68, 136, or 272 bits.) up to 83 million sustained searches per second in 68-bit and 136-bit configurations up to 41.5 million searches per second in 34-bit and 272-bit configurations searches any sub-field in a single cycle offers bit-by-bit and global masking synchronous, pipelined operation up to 31 search engines cascadable without performance degradation when cascaded, the database entries can scale from 124k to 992k depending on the size of the entry glueless interface to industry- standard srams simple hardware instruction interface ieee 1149.1 test access port operating supply voltages include: v dd (operating supply voltage) = 1.8v v ddq (operating supply voltage for i/o) = 2.5 or 3.3v 272 ball, 27mm x 27mm, cavity-up bga figure 1. 272-ball pbga package 272 pbga 27mm x 27mm 1.27mm ball pitch
m7010r 2/67 table of contents description ....................................................................6 overview......................................................................6 performance ...................................................................6 applications....................................................................6 product range (table 1.) . ........................................................6 switch/router implementation using the m7010r (figure 2.) .............................6 signalnames(table2.)..........................................................7 connections (figure 3.) . . . ........................................................8 m7010rblockdiagram(figure4.)..................................................9 maximumrating................................................................10 absolutemaximumratings(table3.) ..............................................10 dc and ac parameters. . .......................................................11 dc and ac measurement conditions (table 4.) . . . ....................................11 m7010r2.5vactestingload(figure5.)...........................................12 m7010r2.5vinputwaveform(figure6.)............................................12 m7010r2.5voutputloadequiv.(figure7.).........................................12 m7010r3.3vactestingload(figure8.)...........................................12 m7010r3.3vinputwaveform(figure9.)............................................12 m7010r3.3voutputloadequiv.(figure10.)........................................12 capacitance (table 5.) . . . .......................................................13 dccharacteristics(table6.) .....................................................13 actimingwaveformswithclk2x(figure11.).......................................14 actimingparameterswithclk2x(table7.) ........................................15 operation.....................................................................16 commandbusanddqbus ......................................................16 databaseentry(dataarrayandmaskarray).........................................16 arbitration logic. . . .............................................................16 pipelineandsramcontrol.......................................................16 fulllogic.....................................................................16 connections descriptions . .......................................................16
3/67 m7010r clocks ........................................................................18 registers.....................................................................18 clocks(figure12.) .............................................................18 registeroverview(table8.)......................................................18 comparandregisters...........................................................18 comparandregisterselectionduringsearchandlearn(figure13.)...................19 maskregisters................................................................18 addressingtheglobalmaskregister(gmr)array(figure14.) ..........................19 search-successful registers. . . .................................................19 search-successful register (ssr) description (table 9.). .............................19 thecommandregister .........................................................20 commandregisterfielddescriptions(table10.).....................................20 search procedure for 32-bit wide prefixes ...................................22 globalmaskregisterpatterns(figure15.) ..........................................22 storinglefthalfofadataormaskarray(figure16.) ...................................22 theinformationregister.........................................................23 informationregisterfielddescriptions(table11.) ....................................23 the read burst address register (rburreg) . . ....................................23 readburstregisterdescription(table12.).........................................23 the write burst address register (wburreg) . ....................................23 writeburstregisterdescription(table13.) ........................................23 thenfaregister..............................................................24 nfaregister(table14.).........................................................24 search engine architecture . .................................................24 dataandmaskaddressing.......................................................24 m7010rdatabaseconfiguration(figure17.).........................................25 bitpositionmatch(table15.).....................................................25 multi-widthconfigurationexample(figure18.) .......................................25 m7010rdataandmaskarrayaddressing(figure19.).................................26 command codes and parameters ..............................................27 commandcodes...............................................................27 commandsandcommandparameters .............................................27 commandcodes(table16.) .....................................................27 commandparameters(table17.) .................................................27 readcommand.................................................................28 singlelocationreadcycletiming(figure20.)......................................29 burstreadofthedataandmaskarrays(blen=4)(figure21.) ........................29 readcommandparameters(table18.)............................................30 dataandmaskarray,sramreadaddressformat(table19.) .........................30 readaddressformatforinternalregisters(table20.)................................30 readaddressformatfordataandmaskarrays(table21.) ............................31
m7010r 4/67 writecommand................................................................31 singlelocationwritecycletiming(figure22.) .....................................32 burstwriteofthedataandmaskarrays(blen=4)(figure23.)........................32 (single)writeaddressformatfordataandmaskarraysorsram(table22.).............33 writeaddressformatforinternalregisters(table23.)...............................33 writeaddressformatfordataandmaskarray(burstwrite)(table24.)................33 search command . .............................................................34 68-bitconfiguration ...........................................................34 hardwarediagramforatablewithasingledevice(68-bitoperation)(figure24.) ...........34 68-bitconfigurationsearchtimingdiagram(onedevice)(figure25.)...................35 right-shift of 68-bit signals for tlsz values (table 25.) . . . .............................36 shiftofssfandssvfromsadr(fordifferenthlatvalues)(table26.)...................36 latency of search from instruction to sram access cycle (68-bit mode) (table 27.) ........36 68-bitlogicalsearch..........................................................37 x68tablewithonedevice(figure26.) .............................................37 136-bitconfiguration ..........................................................38 hardware diagram for a table with one device (136-bit operation) (figure 27.) . . . ..........38 136-bitconfigurationsearchtimingdiagram(onedevice)(figure28.)..................39 right-shift of 136-bit signals for tlsz values (table 28.) . . .............................40 shiftofssfandssvfromsadr(fordifferenthlatvalues)(table29.)...................40 latencyofsearchfrominstructiontosramaccesscycle(136-bitmode)(table30.).......40 136-bitlogicalsearch.........................................................41 x136tablewithonedevice(figure29.) ............................................41 272-bitconfiguration ..........................................................42 hardware diagram for a table with one device (272-bit operation) (figure 30.) . . . ..........42 272-bitconfigurationsearchtimingdiagram(onedevice)(figure31.)..................43 right-shift of 272-bit signals for tlsz values (table 31.) . . .............................44 shiftofssfandssvfromsadr(fordifferenthlatvalues)(table32.)...................44 latencyofsearchfrominstructiontosramaccesscycle(272-bitmode)(table33.).......44 272-bitlogicalsearch.........................................................45 x272tablewithonedevice(figure32.) ............................................45 mixed-sized searches on tables configured with different width using an m7010r device46 multiwidthconfigurationexample(figure33.)........................................46 timingdiagramformixedsearch(onedevice)(figure34.)...........................47 lram and ldev description . . . .................................................48 learncommand ...............................................................48 learncommandtimingdiagram(tlsz=00)(figure35.).............................49 learntimingdiagram(tlsz=1,exceptonlastdevice)(figure36.)....................50 learntimingdiagramondevicenumber7(tlsz=01)(figure37.).....................51 sramwritecyclelatencyfromsecondcycleoflearninstruction(table34.)...........51
5/67 m7010r depth-cascading . .............................................................52 depth-cascadinguptoeightdevices(oneblock) ....................................52 depth-cascading up to 31 devices (4 blocks) ........................................52 depth-cascadingtogenerateafullstateforablock ...............................52 depth-cascadingtoformasingleblock(8devices)(figure38.).........................53 four blocks (31 devices cascaded) search, 68-bit configured with ldev = 1 (figure 39.) ...54 full state generation in a cascaded table (figure 40.) . .............................55 arbitration ...................................................................56 timingdiagramforarbitrationwithinablock(figure41.)...............................56 timingforarbitrationfortwoormoreblocksforthelastdevice(figure42.)................57 sram addressing . .............................................................58 srampioaccess .............................................................58 sram read access for one m7010r device (figure 43.) . .............................59 sramwriteaccessforonem7010rdevice(figure44.) .............................61 srambusaddressgeneration(table35.)..........................................61 right-shift of sram signals for tlsz values (table 36.) . . .............................62 right-shift of sram signals for hlat values (table 37.) . . .............................62 jtag(1149.1)testing ...........................................................62 testaccessportcontrollerinstructions(table38.)....................................62 tapdeviceidregister(table39.) ................................................62 powerdistributionguideline .................................................63 networksearchenginepowerdistribution(figure45.).................................63 partnumbering ...............................................................64 package mechanical information . . . ..........................................65 revisionhistory...............................................................66
m7010r 6/67 description overview the m7010r is a feature-rich, tcam-based hard- ware search engine optimized for networking and communications applications. it incorporates lead- ing-edge associative processing technology (apt, trademark of cypress semiconductor, inc.) and advanced power management. the data ta- ble may be partitioned into up to four (4) quad- rants, allowing the user to configure each quadrant with different table entry widths (x34, x68, x136, or x272-bit). it is also programmable to accelerate performance. performance the m7010r outperforms competitive solutions using software sequential search algorithms in conjunction with srams or asics, or hardware implementation with asics and cams. the latter solution, while faster than a software-based solu- tion, still suffers from performance degradation when depth-cascaded and is unable to scale to next-generation requirements. the m7010r- based solutions overcome all of these drawbacks. applications the performance and features of the m7010r makes it ideal in applications such as enterprise lan switches, broadband switching and routing equipment, supporting multiple data rates from ocC48 and beyond. figure 2 illustrates how a search engine sub- system can be optimized using a host bridge asic, the m7010r, and synchronous or non-syn- chronous srams. it also illustrates how this sys- tem fits into a switch-router implementation. table 1. product range figure 2. switch/router implementation using the m7010r part number operating supply voltage operating i/o voltage speed m7010r-083za1 1.8v 2.5 or 3.3v 83mhz m7010r-066za1 1.8v 2.5 or 3.3v 66mhz program memory switch fabric switch processor network line interfaces system bus host asic sram bank search engine ai04272
7/67 m7010r table 2. signal names note: signal types are: i = input only; i/o = input or output; o = output; and t = tristate 1. ack and eot signals require a pull-down resistor of 47 ohms. symbol type connection name clocks and reset clk2x i master clock phs_l i phase rst_l i reset command and dq bus cmd[8:0] i command bus cmdv i command valid dq[67:0] i/o address/data bus ack (1) t read acknowledge eot (1) t end of transfer ssf t search successful flag ssv t search successful flag valid sadr[21:0] t sram address ce_l t sram chip enable we_l t sram write enable oe_l t sram output enable ale_l t address latch enable cascade interface lhi[6:0] i local hit in lho[1:0] o local hit out bhi[2:0] i block hit in bho[2:0] o block hit out fuli[6:0] i full in fulo[1:0] o full out full o full flag device identification id[4:0] i device identification test access port tdi i test access port s test data in tck i test access port s test clock tdo t test access port s test data out tms i test access port s test mode select trst_l i test access port s reset
m7010r 8/67 figure 3. connections note: this diagram is top view perspective (view through package). sadr 8 sadr 13 sadr 11 sadr 14 sadr 17 sadr 20 sadr 10 sadr 19 sadr 18 sadr 21 sadr 15 sadr 5 sadr 6 sadr 7 sadr 9 sadr 12 sadr 16 sadr 2 sadr 1 sadr 3 sadr 0 sadr 4 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc full eot nc nc nc nc ack nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc lhi6 lhi5 lhi4 lhi1 lho0 lho1 bhi0 bho0 bho1 bho2 fuli0 fuli3 fulo0 fulo1 fuli2 fuli1 fuli4 fuli5 fuli6 bhi2 bhi1 lhi0 lhi2 lhi3 nc nc nc nc nc nc nc nc nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd cmd8 cmd7 cmd5 cmd2 cmd3 cmd1 cmd6 cmd4 cmd0 cmdv dq17 dq15 dq13 dq11 dq9 dq1 dq5 dq7 dq21 dq27 dq31 dq33 dq29 dq25 dq23 dq19 dq35 dq37 dq43 dq53 dq57 dq61 dq63 dq67 dq59 dq55 dq49 dq64 dq62 dq60 dq66 dq58 dq56 dq50 dq48 dq46 dq44 dq42 dq38 dq30 dq36 dq32 dq34 dq28 dq20 dq24 dq22 dq16 dq18 dq8 dq0 dq2 dq4 dq12 dq10 dq14 dq6 dq26 dq40 dq52 dq54 dq51 dq45 dq41 dq39 dq47 dq65 dq3 tdo tms tck tdi id0 id2 id3 id1 id4 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd clk2x we_l oe_l ae_l ce_l phs_l ssf ssv rstl gnd t rst_l right bottom left top ai04270
9/67 m7010r figure 4. m7010r block diagram ai04273 comparand registers[15:0] global mask registers [7:0] information and command register burst read register burst write register next free address register search successful index registers [7:0] (all registers are 68-bit-wide) ta p controller pipeline and sram control arbitration logic command decode and pio access compare/pio data phs_l clk2x rst_l dq [67:0] cmd [8:0] cmdv ack eot cmd compare/pio data address decode priority encode match logic configurable as 32k x 34 16k x 68 8k x 136 4k x 272 data array configurable as 32k x 34 16k x 68 8k x 136 4k x 272 mask array full logic full [6:0] full fulo [1:0] id [4:0] lhi [6:0] bhi [2:0] ssf ssv lho [1:0] bho [2:0] ta p sadr [21:0] oe_l we_l ce_l ale_l
m7010r 10/67 maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 3. absolute maximum ratings note: 1. soldering temperature not to exceed 260 c for 10 seconds (total thermal budget not to exceed 150 c for longer than 30 seconds). symbol parameter value unit t stg storage temperature (v dd off) C 0to70 c t sld (1) lead solder temperature for 10 seconds 235 c v ddq input or output voltages 3.3 v v dd supply voltage C 0.4 to 2.7 v i o output current 100 ma p d power dissipation < 3 w
11/67 m7010r dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 4. dc and ac measurement conditions note: 1. maximum allowable applies to overshoot only (v ddq is 3.3v supply). 2. minimum allowable applies to undershoot only. sym parameter m7010r 2.5v m7010r 3.3v units v dd v dd operating supply voltage 1.7 to 1.9 1.7 to 1.9 v v ddq v ddq voltage for i/o 2.4 to 2.6 3.1 to 3.5 v t a ambient operating temperature 0 to 70 0 to 70 c c l load capacitance 6 6 pf v ih input high voltage (1) 1.7 to v ddq +0.3 2.0 to v ddq + 0.3 v v il input low voltage (2) C 0.3 to 0.7 C 0.3 to 0.8 v supply voltage tolerance 5 5 % t r ,t f input rise and fall times (at 0.3v and 2.7v) 2 (see figure 6, page 12) 2 (see figure 9, page 12) ns input timing reference levels 1.25 1.5 v output timing reference levels 1.25 1.5 v input pulse voltages gnd to 2.5 gnd to 3.3 v input and output timing ref. voltages (see figure 7, page 12) (see figure 10, page 12) v
m7010r 12/67 figure 5. m7010r 2.5v ac testing load figure 6. m7010r 2.5v input waveform figure 7. m7010r 2.5v output load equiv. figure 8. m7010r 3.3v ac testing load figure 9. m7010r 3.3v input waveform figure 10. m7010r 3.3v output load equiv. c l v l = 1.25v 50 z 0 = 50 d out ai04268 +2.5v 90% 10% 90% 10% gnd ai04299 208 192 ai04266 5pf q +2.5v c l v l = 1.5v 50 z 0 = 50 d out ai04269 +3.3v 90% 10% 90% 10% gnd ai04298 158 175 ai04267 5pf q +3.3v
13/67 m7010r table 5. capacitance note: effective capacitance measured with power supply. sampled only, not 100% tested. 1. outputs deselected. table 6. dc characteristics note: 1. valid for ambient operating temperature: t a =0to70 c; v dd =1.8v. symbol parameter test condition min max unit c in input capacitance v in =0v 6pf c io (1) input / output capacitance v out =0v 6pf symb parameter test condition (1) min max unit i li input leakage current v ddq =v ddq (max) 0v v in v ddqmax C 10 +10 a i lo output leakage current v ddq =v ddq (max) 0v v out v ddqmax C 10 +10 a i dd1 1.8v supply current @ v ddmax m7010r i out = 0ma, 83mhz search 1250 ma m7010r i out = 0ma, 66mhz search 1000 ma i dd2 2.5v supply current @ v ddmax m7010r i out = 0ma, 83mhz search 180 ma m7010r i out = 0ma, 66mhz search 150 ma i dd3 3.3v supply current @ v ddmax m7010r i out = 0ma, 83mhz search 300 ma m7010r i out = 0ma, 66mhz search 240 ma v il input low voltage C 0.3 0.8 v v ih input high voltage 2.0 v ddq +0.3 v v ol output low voltage v ddq =v ddq (min) i ol =8ma 0.4 v v oh output high voltage v ddq =v ddq (min) i oh = 8ma 2.4 v
m7010r 14/67 figure 11. ac timing waveforms with clk2x cycle 1 cycle 0 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 12 cycle 9 cycle 11 clk2x signal group 0 signal group 2 signal group 3 signal group 4 signal group 5 phs_l ai04265 signal group 1 signal group 1: phs_l, rst_l signal group 1: dq, cmd, cmdv signal group 2: lhi, bhi, fuli signal group 3: lho, bho, fulo, full signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv signal group 5: dq, ack, eot ticsch tichch tckhov tckhsv tckhshz tckhslz tckhov tihch tisch tisch tisch tihch tihch tihch tckhdz tckhdv
15/67 m7010r table 7. ac timing parameters with clk2x note: 1. valid for ambient operating temperature: t a =0to70 c; v dd =1.8v. 2. values are based on 50% signal levels. 3. basedonanacloadofcl=50pf(seefigure5,page12andfigure8,page12). 4. unless otherwise noted, all values are based on ac load of cl = 50pf (see figure 5, page 12 and figure 8, page 12). 5. these parameters are sampled and not 100% tested. row symbol m7010r-066 m7010r-083 unit description (1) min max min max 1 f clk 133 166 mhz clk2x frequency 2 t clk 7.5 6.0 ns clk2x period 3 t ckhi 3.0 2.4 ns clk2x high pulse (2) 4 t cklo 3.0 2.4 ns clk2x low pulse (2) 5 t isch 2.5 1.8 ns input setup time to clk2x rising edge (2) 6 t ihch 0.6 0.6 ns input hold time to clk2x rising edge (2) 7 t icsch 4.2 3.5 ns cascaded input setup time to clk2x rising edge (2) 8 t ichch 0.6 0.6 ns cascaded input hold time to clk2x rising edge (2) 9 t ckhov 8.5 7.0 ns rising edge of clk2x to lho, fulo, bho, full valid (3) 10 t ckhdv 9.0 7.5 ns rising edge of clk2x to dq valid (4) 11 t ckhdz 8.5 7.0 ns rising edge of clk2x to dq high-z (5) 12 t ckhsv 9.0 7.5 ns rising edge of clk2x to sram bus valid (4) 13 t ckhshz 6.5 6.0 ns rising edge of clk2x to sram bus high-z (4,5) 14 t ckhslz 7.0 6.5 ns rising edge of clk2x to sram bus low-z (4,5)
m7010r 16/67 operation command bus and dq bus cmd[8:0] carries the command and its associated parameter. dq[67:0] is used for data transfer to, and from the data base entries. the database en- tries are comprised of a data field and a mask field which are organized as a data array and a mask array. the dq bus carries the search data dur- ing the search command as well as the address and data during pipelined i/o (pio) read/write operations, of the data array, mask array, and in- ternal registers. the dq bus also can carry the ad- dress information for the pio accesses to the sram. database entry (data array and mask array) each database entry comprises a data field and a mask field. the resultant value of the entry is a log- ical and of the corresponding data and mask bits and can take logical values of '1,' '0' and 'x' (don t care), depending on the value in the mask bit. the on-chip priority encoder selects the first matching entry in the database which is nearest to location 0. arbitration logic when multiple (silicon) search engines are cas- caded to create large databases, the data being searched is presented to all search processors si- multaneously in the cascaded system. when more than one device has duplicate entries, the arbitra- tion logic on the search engine with the matching entry which is closest to address 0 of the cascaded database, will be selected to drive the sram bus. pipeline and sram control pipeline latency is added to give enough time to the arbitration logic in a cascaded system to deter- mine the index with the highest priority. the pipe- line logic adds latency to the sram access cycles and the ssf and ssv signals to align them to the host asic receiving the associated data. refer to table 27, page 36 for details. full logic bit[0] in each of the 68-bit entries has a special purpose for the learn command (0 = empty, 1 = full). when all the data entries have bit[0] set to '1,' the database asserts the full flag, indicating that all the search engines in the depth-cascaded ar- ray are full. connections descriptions master clock (clk2x). the m7010r samples all of the control and data signals on the positive edge of clk2x when phs_l is low. phase (phs_l). this signal runs at half the fre- quency of clk2x and generates an internal clock from clk2x (see figure 12, page 18). reset (rst_l). driving rst low initializes the device to a known state. command bus (cmd[8:0]. [1:0] specifies the command; [8:2] contains the command parame- ters. the descriptions of individual commands ex- plains the details of the parameters. the encoding of commands based on the [1:0] field are: C 00: pio read C 01: pio write C 10: search C 11: learn command valid ( cmdv) . qualifies the cmd bus as follows: C 0: no command C 1: command address/data bus ( dq[67:0]) . carries the read and write address as well as the data during register, data, and mask array operations. it car- ries the compare data during search opera- tions. it also carries the sram address during sram pio accesses. read acknowledge (ack). indicates that valid data is available on the dq bus during register, data, and mask array read operations, or the data is available on the sram data bus during sram read operations. note: ack signals require a pull-down resistor of 47 . end of transfer (eot). indicates the end of burst transfer during read or write burst oper- ations. note: eot signals require a pull-down resistor of 47 ohms. search successful flag (ssf). when assert- ed, this signal indicates that the device is the glo- bal winner in a search operation. search successful flag valid (ssv). when asserted, this signal qualifies the ssf signal. sram address (sadr[21:0]). this bus con- tains address lines to access off-chip srams that contain associative data. see table 35, page 61 for the details of the generated sram address. sram chip enable (ce_l). this is chip enable control for external srams. when more than one device is cascaded, ce_l of all devices must be connected. sram write enable (we_l). this is write enable control for external srams. when more than one device is cascaded, we_l of all devices must be connected. sram output enable (oe_l). this is output enable control for external srams. only the last device drives this signal (with the lram bit set).
17/67 m7010r address latch enable (ale_l). when this sig- nal is low, the addresses on the sram address bus have been validated. when more than one de- vice is cascaded, the ale_l of all devices must be connected. local hit in (lhi[6:0]). these pins depth-cas- cade the device to form a larger table size. one signal of this bus is connected to the lho[1] or lho[0] of each of the upstream devices in a block. connect all unused lhi pins to a logic '0.' (for more information, see depth-cascading, page 52.) local hit out (lho[1:0]). lho[1] and lho[0] are the same logical signal. lho[1] or lho[0] is connected to one input of the lhi bus of up to four downstream devices (in a block that contains up to eight devices; for more information, see depth- cascading, page 52.) block hit in (bhi[2:0]). inputs from the previous bho[2:0] are tied to the bhi[2:0] of the current de- vice (see depth-cascading, page 52). in a four-block system, the last block can contain only seven devices because the id code 11111 is used for broadcast access. block hit out (bho[2:0]). outputs from the cur- rent device are connected to the bhi[2:0] of the next device (see depth-cascading, page 52). full in (fuli[6:0]). each signal in this bus is con- nected to fulo[0] or fulo[1] of an upstream de- vice to generate the full flag for the depth- cascaded block. for more information, see depth-cascading, page 52 to generate full for a block section. full out (fulo[1:0]). fulo[1] and fulo[0] are the same logical signal. one of these two signals must be connected to the fuli of up to four down- stream devices in a depth-cascaded table. bit [0] in the data array indicates if the entry is full (1) or empty (0).this signal is asserted if all of the bits in the data array are '1s.' refer to depth-cascading to generate a full state for a block, page 52. full flag (full). when asserted, this signal in- dicates that the table consisting of many depth- cascaded devices is full. device identification (id[4:0]). the binary-en- coded device id for a depth-cascaded system starts at 00000 and goes up to 11110. 11111 is re- served for a special broadcast address that se- lects all cascaded (silicon) search engines in the system. on a broadcast read-only, the device with the ldev bit set to '1' responds. test data in (tdi). this is the test access port s test data in. test clock (tck). this is the test access port s test clock. test data out (tdo). this is the test access port s test data out. test mode select (tms). this is the test ac- cess port s test mode select. test reset (trst_l). this is the test access
m7010r 18/67 clocks the m7010r receives a clock (clk2x) signal and phase (phs_l) signal. the phase (phs_l) di- vides the clk2x signal to generate the internal clock (clk), as shown in figure 12. the clk2x and clk signals are used for internal operations. registers all the m7010r registers are 68 bits wide. the m7010r contains 32 comparand storage regis- ters, 16 global mask registers, 8 search-suc- cessful index registers, command, information, burst read, burst write, and next free address registers. table 8 provides a register overview of all the registers. the registers are ordered in as- cending address order. comparand registers the device contains thirty-two 68-bit comparand registers dynamically selected in every search operation to store the comparand presented on the dq bus. the learn command will also use these registers when it is executed. the m7010r stores the search command s cycle a com- parand in the even-number register and the cycle b comparand in the odd-numbered register, as shown in figure 13, page 19. mask registers the device contains sixteen (8 pairs) 68-bit global mask registers dynamically selected in every search operation to select the search sub- field (see figure 14, page 19). the three-bit gmr index supplied on the cmd bus applies eight pairs of global masks during the search and write operations, also shown in figure 14. note: in 68-bit search and write operations, the host asic must program the even and odd mask register with the same values, and the m7010r uses even-numbered mask registers as global masks. each mask bit in the global mask registers is used during search and write operations. in search operations, setting the mask bit to '1' en- ables compares; setting the mask bit to '0' dis- ables compares (forced match) at the current bit position. in write operations to the data or mask array, setting the mask bit to '1' enables writes; setting the mask bit to '0' disables writes at the corresponding bit position. figure 12. clocks note: any reference to clk cycles means 2 cycles of the signal, clk2x. 1. clk is an internal signal. the period for this clock is specified in table 7, page 15. table 8. register overview address abbreviation type name 0 C 31 comp0 C 31 r 32 comparand registers. stores comparands from the dq bus for learning later. 32 C 47 masks rw 16 global mask registers array. 48 C 55 ssr0 C 7 r 8 search successful index registers. 56 command rw command register. 57 info r information register. 58 rburreg rw burst read register. 59 wburreg rw burst write register. 60 nfa r next free address register. 61 C 63 CC reserved clk2x phs_l cl k (1) ai04274
19/67 m7010r figure 13. comparand register selection during search and learn figure 14. addressing the global mask register (gmr) array search-successful registers the device contains eight search-successful registers (ssrs) to hold the index of the location where a successful search occurred. the format of each register is described in table 9. the search command specifies which ssr stores the index of a specific search command in cy- cle b of the search instruction. after the index location is specified, the host asic can use this register to access that data array, mask array, or external sram using the index as part of the address (see sram addressing, page 58). the device with a valid bit set performs a read or write operation. all other devices suppress the operation. table 9. search-successful register (ssr) description 13 5 0 68 68 1 0 3 2 5 4 7 6 30 31 0 15 1 a ddre ss index ai04275 13 5 0 68 68 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 0 1 6 7 2 5 4 3 a ddre ss index ai04276 search and write command global mask selection field range initial value description index [13:0] x index. this is the address of the 68-bit entry where a successful search occurs. the device updates this field if it has a successful search. in 136-bit, the lsb is '0;' in a 272-bit configuration, the two lsbs are '00.' the index updates if the device is either a local or global winner in a search operation. C [30:14] 0 reserved. valid [31] 0 valid. the device sets this bit to '1' if it is a global winner (first device downstream with a hit) in a search operation, in a depth-cascaded configuration. C [67:32] 0 reserved.
m7010r 20/67 the command register table 10. command register field descriptions field range initial value description srst [0] 0 software reset. if '1,' this bit resets the device, with the same effect as the hardware reset. internally, it generates a reset pulse lasting for eight clk cycles. this bit automatically resets to a '0' during the reset cycle. deve [1] 0 device enable. if '0,' it keeps the sram bus (sadr, we_l, ce_l, oe_l, and ale_l), ssf, and ssv signals in a tri-state condition and forces the cascade interface output signals lho[1:0] and bho[2:0] to '0.' it also keeps the dq bus in input mode. the purpose of this bit is to make sure that there is no bus contention when the devices power-up in the system. tlsz [3:2] 01 table size. the host asic must program this field to configure the chips into a table of a certain size. this field affects the pipeline latency of the search and learn operations as well as the read and write accesses to the sram (sadr[21:0], ce_l, oe_l, we_l, ale_l, ssv, ssf, and ack). once programmed, the search latency stays constant. latency # clk cycles 00: 1 device 4 01: 2-8 devices 5 10: 9-31 devices 6 11: reserved hlat [6:4] 000 latency of hit signals. this field adds latency to the ssf, ssv, and ack signals by the following number of clk cycles during search and ack during an sram read access. 000: 0 100: 4 001: 1 101: 5 010: 2 110: 6 011: 3 111: 7 ldev [7] 0 last device in the cascade. when set, this device is the last device in the depth-cascaded table and is the default driver for the ssf and ssv signals. in the event of a search failure, the device with this bit set drives the hit signals as follows: ssf = 0, ssv = 1 during non-search cycles, the device with this bit set drives the signals as follows: ssf = 0, ssv = 0 lram [8] 0 last device on this sram bus. when set, this device is the last device on the sram bus in the depth-cascaded table and is the default driver for the sadr, ce_l, we_l, and ale_l signals. in cycles where no m7010r device (in a depth-cascaded table) drives these signals, the signals are driven as follows: sadr = 22 h3fffff, ce_l = 1, we_l = 1, and ale_l = 1. oe_l is always driven by the device for which this bit is set.
21/67 m7010r cfg [16:9] 0000 0000 database configuration. the device is internally divided into four quadrants of 8k x 68, each of which can be configured as 4k x 68, 2k x 136, or 1k x 272 as follows: 00: 4k x 68 01: 2k x 136 10: 1k x 272 11: reserved bits [10:9] apply to configuring the 1st quadrant in the address space. bits [12:11] apply to configuring the 2nd quadrant in the address space. bits [14:13] apply to configuring the 3rd quadrant in the address space. bits [16:15] apply to configuring the 4th quadrant in the address space. [67:17] 0 reserved. field range initial value description
m7010r 22/67 search procedure for 32-bit wide prefixes the global mask register is used for 32-bit wide data paths as follows: writing a '1' in the global mask register allows data to be written into the m7010r. a '0' in the glo- bal mask register disallows data modification. in- formation is written into the left half of the 68-bit word search engine as long as space for 34 bits of data is available and then into the right half of the search engine. 32-bit data can be entered in two cycles. the first step is to write into two of the eight global mask registers with the patterns shown in figure 15. writing this data using global mask register 1 allows the left half of the data array to be com- pletely filled. figure 16 shows bits 67 through 36 in the left sec- tion of the data array representing 32-bits of data. bits 35 and 34 shown separately can be defined by the user for table management. in this applica- tion 34-bit operation occurs in each half-section of the data and mask arrays of the search engine. the left half is filled first, then the right. not all lo- cations have to be filled. search operations are performed twice, once on the left half and then on the right half. note that a '1' in the global mask register enables a compare during a search operation and a '0' forces a match condition regardless of the state of the data bit. the search throughput for 34-bit operations is half of the 68-bit operations. a search is performed by using the global mask register 0 for the left half of the 68-bit, then another search is performed using global mask register 1 for the right half of the 68-bit word. the order is important, as the left half has a higher priority than the right half. for example, if a search on the left half produces a match and a search on the right half also produc- es a match, then in that case, the left half is a high- er priority. so if only one unique match exists in a particular system, then a match on the left side may alleviate the need to do a search on the right half of the data array. figure 15. global mask register patterns figure 16. storing left half of a data or mask array 111 1000 0 000 0111 1 register 0 register 1 bits 67 3433 0 ai04277 bits 67 36 35 34 33 2 1 0 ai04278
23/67 m7010r the information register table 11. information register field descriptions the read burst address register (rburreg) these read burst address register fields must be programmed before burst read (see table 12). the write burst address register (wburreg) these write burst address register fields must be programmed before burst write (see table 13). table 12. read burst register description table 13. write burst register description field range initial value description revision [3:0] 0001 revision number. this is the current device revision number. numbers start from one and increment by one for each revision of the device. implemen- tation [6:4] 000 this is the m7010r implementation number. reserved [7] 0 reserved. device id [15:8] 00000001 this is the device identification number. mfid [31:16] 1101_1100_ 0111_1111 manufacturer id. this field is the same as the manufacturer id and continuation bits. [67:32] reserved. field range initial value description aadr [13:0] 0 address. this is the starting address of the data array or mask array during a burst read operation. it automatically increments by 1 for each successive read of the data array or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:14] reserved. blen [27:19] 0 length of burst access. the device provides the capability to read from 4 up to 511 locations in a single burst. the blen decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [67:28] reserved. field range initial value description aadr [13:0] 0 address. this is the starting address of the data array or mask array during a burst write operation. it automatically increments by 1 for each successive write of the data array or mask array.it increments by 1 for each successive read of the data array or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:14] reserved. blen [27:19] 0 length of burst access. the device provides the capability to write from 4 up to 511 locations in a single burst. the blen decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [67:28] reserved.
m7010r 24/67 the nfa register bit [0] of each 68-bit data entry is a special bit des- ignated for use in the operation of the learn command. in 68-bit configurations, the bit[0] indi- cates whether a location is full (bit set to '1') or empty (bit set to '0'). every write/learn com- mand loads the address of first 68-bit location that contains a 0 in the entry s bit[0]. this is stored in the nfa register. if all the bits in a device are set to '1,' the m7010r asserts fulo[1:0] to '1.' in a 136-bit configuration, the lsb of this register is always set to '0.' the host asic must set bit 0 and bit 68 in a 136-bit word to either '0' or '1' to in- dicate full/empty status for a 136-bit entry. note: both bits 0 and bit 68 must be set to '0' or '1' (e.g., '10' or '01' settings are invalid). table 14. nfa register search engine architecture the m7010r consists of 16k x 68-bit storage cells referred to as data bits. there is a mask cell cor- responding to each data cell. figure 17 shows the three organizations of the device based on the val- ue of cfg bits in the command register. during a search operation, the search data bit(s),dataarraybit(d),maskarraybit(m)and the global mask bit (g) are used in the following manner to generate a match at that bit position (see table 15, page 25). the entry with all matched bit positions results in a successful search in the m7010r. in order for a successful search to make the device the local winner in the search operation, all 68-bit posi- tions within a device must generate a match for a 68-bit entry in 68-bit-configured quadrants, or all 136-bit positions must generate a match for two consecutive even and odd 68-bit entries in quad- rants configured as 136 bits, or all 272-bit posi- tions must generate a match for four consecutive entries aligned to four entry-page boundaries of 68-bit entries in quadrants configured as 272 bits. an arbitration mechanism using a cascade bus de- termines the global winning device among the lo- cal winning devices in a search cycle. the global winning device drives the sram bus, ssv, and the ssf signals. in the case of a search failure, the device(s) with ldev and lram bits set drive the sram bus, ssf, and ssv signals. the m7010r may be partitioned into up to four (4) quadrants of different widths (e.g., 34, 68, 136, or 272 bits), even within the same chip (see applica- tion notes an1338 and an1339). figure 18 shows a sample configuration of different widths. data and mask addressing figure 19, page 26 shows the m7010r data array and mask array addressing procedure. the data array and mask array addresses differ only in one bit in the address cycle of the read and write commands. address 67 - 14 13 - 0 60 reserved index
25/67 m7010r figure 17. m7010r database configuration table 15. bit position match figure 18. multi-width configuration example data data data masks masks masks 16 k cfg = 00000000 cfg = 01010101 cfg = 10101010 68 136 272 8 k 4 k ai04264 g m s d match 0xxx1 10xx1 11001 11010 11100 11111 4 k 4 k 2 k 1 k 68 68 136 272 cfg = 10010000 ai04244
m7010r 26/67 figure 19. m7010r data and mask array addressing cfg = 0 000 00 00 cfg = 10101010 67 0 0 1 2 3 16383 27 1 0 3 2 1 0 7 6 5 4 16380 16381 16382 16383 68 cfg = 010 10 10 1 135 0 1 0 3 2 5 4 7 6 16382 16383 (6 8-bit co nfigu ration ) (27 2-bit conf ig urat io n) (1 36 -b it con figura tion) 16 k 4k 8k 68 68 68 68 68 68 ai04263
27/67 m7010r command codes and parameters a master device, such as an asic controller, is- sues commands to the m7010r using the cmdv signal and the cmd bus. the following subsec- tions describe the functions of the commands. command codes the m7010r implements four basic commands shown in table 16. the command code must be presented to cmd[1:0] while keeping the com- mand valid (cmdv) signal high for two clk2x cy- cles. these two clk2x cycles are designated as cycle a and cycle b. the cmd[8:2] field pass- es the parameters of the command in clk2x cy- cles a and b. the controller asic must align the instructions with the clk2x signal. commands and command parameters table 17 lists the cmd bus fields that contain the m7010r command parameters as well as their re- spective cycles. table 16. command codes table 17. command parameters note: the sram address bit sadr [19] in the command bit c6 will not be passed to the sram (see table 28). 1. the 272-bit configuration does not support the learn instruction. cmd code command description 00 read reads one of the following: data array, mask array, device registers, or external sram. 01 write writes one of the following: data array, mask array, device registers, or external sram. 10 search searches the data array for a desired pattern using the specified register from the global mask register array and local mask associated with each data cell. 11 learn the device has internal storage for up to 16 comparands that it can learn. the device controller can insert these entries at the next free address (as specified by the nfa register) using the learn instruction. cmd cyc 8 7 6 5 4 3 2 1 0 read a sadr[21] sadr[20] sadr[19] 0 0 0 0 = single 1 = burst 00 b0 0 0 000 0 = single 1 = burst 00 write a sadr[21] sadr[20] sadr[19] gmr index[2:0] 0 = single 1 = burst 01 b 0 0 0 gmr index[2:0] 0 = single 1 = burst 01 search a sadr[21] sadr[20] sadr[19] gmr index[2:0] 68-bit or 136-bit: 0 272-bit: 1 in 1st cycle 0 in 2nd cycle 10 b successful search register index[2:0] comparand register index 1 0 learn (1) a sadr[21] sadr[20] sadr[19] comparand register index 1 1 b0 0 mode 0: 68-bit 1: 136-bit comparand register index 1 1
m7010r 28/67 read command thereadcanbeasinglereadofadataarray,a mask array, an sram, or a register location (cmd[2] = 0). it can be a burst read (cmd[2] = 1) using an internal auto-incrementing address regis- ter (rburadr) of the data or mask array loca- tions (see table 18, page 30 and table 19, page 30 for formats). a single-location read operation takes six cycles, as shown in figure 20, page 29. the burst read adds two cycles for each successive read. the sadr[21:19] bits supplied in the read instruction cycle a drives sadr[21:19] signals during the pio read of an sram location. the single read operation takes six clk cycles, in the following sequence: C cycle 1: the host asic applies the read in- struction on the cmd[1:0] (cmd[2] = 0), using cmdv = 1, and the dq bus supplies the ad- dress, as shown in table 19, page 30 and table 20, page 30. the host asic selects the device for which id[4:0] matches the dq[25:21] lines. if dq[25:21] = 11111, the host asic selects the m7010r with the ldev bit set. the host asic also supplies sadr[21:19] on cmd[8:6] in cy- cle a of the read instruction if the read is di- rected to the external sram. C cycle 2: the host asic releases the dq[67:0] bus to a tri-state condition. C cycle 3: the host asic keeps dq[67:0] bus in a tri-state condition. C cycle 4: the selected device starts to drive the dq[67:0] bus and drives the ack signal from z to low. C cycle 5: the selected device drives the read data from the addressed location on the dq[67:0] bus and drives the ack signal high. C cycle 6: the selected device floats the dq[67:0] bus and drives the ack signal low. at the termination of cycle 6, the selected device releases the ack line to a tri-state condition. the read instruction is complete, and a new opera- tion can begin. the burst read operation lasts 4 + 2n clk-cycles (where n stands for the number of accesses in the burst specified by the blen field of the rbur- reg) in the sequence shown in figure 21, page 29. this operation assumes that the host asic has programmed the rburreg with the starting address (addr) and the length of transfer (blen) before initiating the burst read command. C cycle 1: the host asic applies the read in- struction on the cmd[1:0] (cmd[2] = 1), using cmdv=1 and the address supplied on the dq bus, as shown in table 21, page 31. the host asic selects the device for which id[4:0] match- es the dq[25:21] lines. if dq[25:21] = 11111, the host asic selects the m7010r with the ldev bit set. C cycle 2: the host asic floats dq[67:0] to a tri- state condition. C cycle 3: the host asic keeps dq[67:0] bus in a tri-state condition. C cycle 4: the selected device starts to drive the dq[67:0] bus and drives ack, and eot from z to low. C cycle 5: the selected device drives the read data from the addressed location on the dq[67:0] bus and drives the ack signal high. note: cycles four and five repeat for each addi- tional access until all the accesses specified in the burst length (blen) field of rburreg are complete. on the last transfer, the m7010r drives the eot signal high. C cycle (4 + 2n): the selected device drives the dq[67:0] to 3-state condition and drives the ack and the eot signals low. at the termination of cycle 4 + 2n, the selected de- vice floats the ack line to 3-state condition. the burst read instruction is complete, and a new op- eration can begin (see table 21, page 31 for burst read address formats).
29/67 m7010r figure 20. single location read cycle timing figure 21. burst read of the data and mask arrays (blen = 4) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack dq phs_ l ai04282 read cmd[8:2] a b ad dress x data cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 11 cycle 12 cycle 9 clk2x cmdv cmd[1:0] ack eot dq phs_ l ai04283 read cmd[8:2] a b ad dress ff data0 ff data1 ff data2 ff data3
m7010r 30/67 table 18. read command parameters table 19. data and mask array, sram read address format note: 1. | stands for logical or operation, and {} stands for concatenation operator. table 20. read address format for internal registers cmd parameter cmd[2] read command description 0 single read reads a single location of the data array, mask array, external sram, or device registers. all access information is applied on the dq bus. 1 burst read reads a block of locations from the data array or mask array as a burst. the internal register (rburadr) specifies the starting address and the length of the data transfer from the data array or mask array, and it auto-increments the address for each access. all other access information is applied on the dq bus. note: the device registers and external sram can only be read in single-read mode. dq [67:30] dq [29] dq [28:26] dq [25:21] dq [20:19] dq [18:14] dq [13:0] reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 00: data array reserved if dq[29] is '0,' this field carries address of data array location. if dq[29] is '1,' the successful search register specified on dq[28:26] supplies the address of the data array location: {ssr[13:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 01: mask array reserved if dq[29] is '0,' this field carries address of mask array location. if dq[29] is '1,' the successful search register specified on dq[28:26] supplies the address of the mask array location: {ssr[13:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 10: external sram reserved if dq[29] is '0,' this field carries address of sram location. if dq[29] is '1,' the successful search register specified on dq[28:26] supplies the address of the sram location. dq[67:26] dq[25:21] dq[20:19] dq[18:6] dq[5:0] reserved id 11: register reserved register address
31/67 m7010r table 21. read address format for data and mask arrays write command thewritecanbeasinglewriteofadataarray, mask array, register, or external sram location (cmd[2] = 0). it can also be a burst write (cmd[2] = 1) using an internal auto-incrementing address register (wburadr) of the data array or mask array locations (see table 23, page 33 for format). a single-location write is a three-cycle operation, shown in figure 22, page 32. the burst write adds one extra cycle for each successive location write. the write operation sequence is as follows: C cycle 1a: the host asic applies the write in- structiontocmd[1:0](cmd[2]=0),usingcm- dv=1 and the address supplied on the dq bus, as shown in table 22, page 33. the host asic also supplies the index to the global mask reg- ister (gmr) to mask the write to the data ar- rayormaskarraylocationincmd[5:3].for sram writes, the host asic must supply sadr[21:19] on cmd[8:6]. C cycle 1b: the host asic continues to apply the write instruction to cmd[1:0] (cmd[2] = 0) using cmdv = 1 and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in cmd[5:3]. the host asic selects the device where id[4:0] matches the dq[25:21] = 11111. C cycle 2: the host asic drives the dq[67:0] with the data to be written to the data array, mask array, external sram, or register location of the selected device. C cycle 3: idle cycle. at the termination of this cy- cle, another operation can begin. the burst write operation lasts for (n + 2) clk cycles, where n signifies the number of accesses in the burst as specified in the blen field of the wburreg register (see figure 23, page 32). this operation assumes that the host asic has programmed the wburreg with the starting ad- dress (addr) and the length of transfer (blen) before initiating the burst write command (see table 24, page 33 for format). the sequence is as follows: C cycle 1a: the host asic applies the write in- struction on the cmd[1:0] (cmd[2] = 1), using cmdv = 1 and the address supplied on the dq bus, as shown in table 23, page 33. the host asic also supplies the index to the global mask register to mask the write to the data or mask array locations in cmd[5:3]. C cycle 1b: the host asic continues to apply the write instruction to cmd[1:0] (cmd[2] = 0) using cmdv = 1 and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in cmd[5:3]. the host asic selects the device where id[4:0] matches the dq[25:21] = 11111. C cycle 2: the host asic drives the dq[67:0] withthedatatobewrittentothedataarrayor mask array location of the selected device. the host asic writes the data on the dq[67:0] bus only to the subfield that has the corresponding mask bit set to '1' in the global mask register specified by the index cmd[5:3] and supplied in cycle 1. C cycles 3 to n + 1: the host asic drives dq[67:0] with the data to be written to the next data array or mask array location (addressed by the auto-increment aadr field of the wbur- reg register) of the selected device. the host asic writes the data on the dq[67:0] bus only to the subfield that has the correspond- ing mask bit set to '1' in the global mask register specified by the index cmd[5:3] and supplied in cycle 1. the m7010r drives the eot signal low from cycle 3 to cycle n; the m7010r drives the eotsignalhighincyclen+1(nisspecifiedin the blen field of the wburreg). C cycle n + 2: the m7010r drives the eot signal low. at the termination of the cycle n + 2, the m7010r floats the eot signal to a 3-state, and a new instruction can begin. dq[67:26] dq[25:21] dq[20:19] dq[18:14] dq[13:0] reserved id 00: data array reserved do not care. these 14 bits come from the internal register (rburadr) which increments for each access. reserved id 01: mask array reserved do not care. these 14 bits come from the internal register (rburadr) which increments for each access.
m7010r 32/67 figure 22. single location write cycle timing figure 23. burst write of the data and mask arrays (blen = 4) cycle 1 cycle 2 cycle 3 cycle 4 cycle 0 clk2x cmdv cmd[1:0] dq phs_ l ai04284 write cmd[8:2] a b ad dress data x cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] eot dq phs_ l ai04285 write cmd[8:2] a b ad dress data0 data1 data2 data3 x
33/67 m7010r table 22. (single) write address format for data and mask arrays or sram note: 1. | stands for logical or operation, and {} stands for concatenation operator. table 23. write address format for internal registers table 24. write address format for data and mask array (burst write) dq [67:30] dq [29] dq [28:26] dq [25:21] dq [20:19] dq [18:14] dq [13:0] reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 00: data array reserved if dq[29] is '0,' this field carries the address of the data array location. if dq[29] is '1,' the ssr specified on dq[28:26] is used to generate the address of the data array location: {ssr[13:2], ssr[1] | dq[1], ssr[0] | dq[0]}. (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 01: mask array reserved if dq[29] is '0,' this field carries address of the mask array location. if dq[29] is '1,' the ssr specified on dq[28:26] is used to generate the address of the data array location: {ssr[13:2], ssr[1] | dq[1], ssr[0] | dq[0]}. (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 10: external sram reserved if dq[29] is '0,' this field carries address of the data sram location. if dq[29] is '1,' the ssr specified on dq[28:26] is used to generate the address of the data array location: {ssr[13:2], ssr[1] | dq[1], ssr[0] | dq[0]}. (1) dq[67:26] dq[25:21] dq[20:19] dq[18:6] dq[5:0] reserved id 11: register reserved register address dq [67:26] dq [25:21] dq [20:19] dq [18:14] dq [13:0] reserved id 00: data array reserved don t care. these 14 bits come from the internal register (wburadr), which increments with each access. reserved id 01: mask array reserved don t care. these 14 bits come from the internal register (wburadr), which increments with each access.
m7010r 34/67 search command the m7010r search engine can be configured in three ways: 1. 68-bit 2. 136-bit 3. 272-bit 4. mixed-sized searches on tables config- ured with different widths 68-bit configuration figure 25, page 35 shows the timing diagram for a search operation in the 68-bit-configured table (one device only). this illustration assumes that the host asic has programmed tlsz to '00,' hlat to '000,' lram to '1,' and ldev to '1' in the command register. the hardware diagram for this search subsystem is shown in figure 24. C cycle a: thehostasicdrivescmdvhighand applies the search command code (10) on cmd[1:0]. cmd[5:3] must be driven by the in- dex to the global mask register pair for use in the search operation. cmd[8:6] signals must be driven by the same bits that will be driven on sadr[21:19] by this device if it has a hit. dq[67:0] must be driven with the data to be compared. cmd[2] signal must be driven to log- ic '0.' C cycle b: the host asic continues to drive cmdv high and to apply the search com- mand (10) on cmd[1:0]. cmd[5:2] must be driv- en by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag. the dq[67:0] continues to carry the 68-bit data to be com- pared. note: in the 68-bit configuration, the host asic must supply the same data on dq[67:0] during cycles a and b. the even and odd gmr pairs selected for the compare must be programmed with the same value. the search command is a pipelined operation and executes a search at half their rate of fre- quency of clk2x for 68-bit searches in x68-con- figured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from 68-bit search command cycle (= two clk2x cycles) is shown in table 27, page 36. the timing diagram for all sram interface signals, ssv, and ssf shift to the right for different values of tlsz, as specified in table 25, page 36 and ta- ble 26, page 36. in addition, ssv and ssf shift to the right for dif- ferent values of hlat, as specified in table 26, page 36. 68-bit configuration with ldev = 1. the de- vice is configured to be the last in the depth-cas- caded table by setting ldev to '1' in the command register. the device with ldev set to '1' drives the ssf and ssv signals in cycles when all up- stream devices do not drive these signals. the m7010r with its ldev bit set drives ssf and ssv during a search with a miss or with non-search commands (see the ldev bit definition in table 10, page 20). 68-bit configuration with lram = 1. setting lram to '1' in the command register configures the device to be the last on the sram bus. in a cy- cle where the upstream device does not drive the sram bus, the last device of the sram bus (with lram = 1) drives the bus (sadr, ce_l, we_l, ale_l) when they are active. when set to '1,' the lram bit sets the default driver for the sram con- trol signals (sadr, ce_l, we_l, and ale_l). figure 24. hardware diagram for a table with a single device (68-bit operation) dq[67:0] cmdv, cmd[8:0] ssf, ssv sram lho[1] bhi[2:0] bhi[2:0] lhi 3210 m7010r lho[0] 654 ai07040
35/67 m7010r figure 25. 68-bit configuration search timing diagram (one device) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ale_l, ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l ai04286 a b a b a b a b dq d1 d2 d3 a1 1 1 11 11 11 11 0 0 0 0 0 0 0 0 0 1 0 0 0 a3 d4 01 01 01 01 hit miss hit miss cfg = 00000000, hlat = 000, tlsz = 00, lram = 1, ldev = 1 search1 search2 search3 search4
m7010r 36/67 table 25. right-shift of 68-bit signals for tlsz values table 26. shift of ssf and ssv from sadr (for different hlat values) table 27. latency of search from instruction to sram access cycle (68-bit mode) tlsz number of clk cycles 00 0 01 1 10 2 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 # of devices max table size latency in clk cycles 1 (tlsz = 00) 16k x 68-bit 4 2 C 8 (tlsz = 01) 128k x 68-bit 5 9 C 31 (tlsz = 10) 496k x 68-bit 6
37/67 m7010r 68-bit logical search the logical, 68-bit search operation is shown in figure 26. the entire table of 68-bit entries is com- pared to a 68-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 68-bit word specified by the identical value in both even and odd gmr pairs selected by the gmr index in the command s cycle a. the 68-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs selected by the comparand register index in the com- mand s cycle b. in a x68 configuration, only the even comparand register can subsequently be used by the learn command. the word k (pre- sented on the dq bus in both cycles a and b of the command) is compared with each entry in the table, starting at location 0. the first matching entry s location, address l, is the winning ad- dress that is driven as part of the sram address on the sadr[21:0] lines. figure 26. x68 table with one device comparand register (even) comparand register (odd) 67 0 k cfg = 00000000 0 1 2 3 16383 (68-bit configuration) location address l k 67 0 k gmr 67 0 ai07041 (first matching entry)
m7010r 38/67 136-bit configuration figure 28, page 39 shows the timing diagram for the search operation in the 136-bit table (cfg = 01010101) consisting of a single device for one set of parameters: tlsz = 00, hlat = 001, lram = 1, and ldev = 1. the hardware diagram for the search subsystem is shown in figure 27. the following is the operation sequence for a sin- gle, 136-bit search command. C cycle a: the host asic drives the cmdv high and applies the search command code (10) to cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[21:19] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) to be compared against all even loca- tions. the cmd[2] signal must be driven to logic '0.' C cycle b: the host asic continues to drive the cmdv high and applies search command code (10) on cmd[1:0]. cmd[5:2] must be driv- en by the index to the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven by the index of the ssr that will be used for storing the address of the matching entry and hit flag. the dq[67:0] is driven with 68-bit data ([67:0]), compared to all odd loca- tions. note: for 136-bit searches, the host asic must supply two distinct, 68-bit data words on dq[67:0] during cycles a and b. the even- numbered gmr of the pair specified by the gmr index is used for masking the word in cy- cle a. the odd-numbered gmr of the pair spec- ified by the gmr index is used for masking the word in cycle b. the search command is a pipelined operation that executes searches at half the rate of the fre- quency of clk2x for 136-bit searches in x136-bit- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 136-bit search command cycle (two clk2x cycles) is shown in table 30, page 40. the timing diagram for all sram interface signals, ssv, and ssf shift to the right for different values of tlsz, as specified in table 28, page 40. in addition, ssv and ssf shift to the right for dif- ferent values of hlat, as specified in table 29, page 40. the result of the search operation appears as an sram read cycle with a pipelined latency. it is specified as shown in table 30, page 40. figure 27. hardware diagram for a table with one device (136-bit operation) dq[67:0] cmdv, cmd[8:0] ssf, ssv sram lho[1] bhi[2:0] bhi[2:0] lhi 3210 m7010r lho[0] 654 ai07040
39/67 m7010r figure 28. 136-bit configuration search timing diagram (one device) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ale_l, ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l ai04287 a b a b a b a b a b a b a b a b dq d1 d2 d3 a1 1 1 11 11 11 11 0 0 0 0 0 0 0 0 0 1 0 0 0 a3 d4 01 01 01 01 hit miss hit miss cfg = 01010101, hlat = 001, tlsz = 00, lram = 1, ldev = 1 search1 search2 search3 search4
m7010r 40/67 table 28. right-shift of 136-bit signals for tlsz values table 29. shift of ssf and ssv from sadr (for different hlat values) table 30. latency of search from instruction to sram access cycle (136-bit mode) tlsz number of clk cycles 00 0 01 1 10 2 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 # of devices max table size latency in clk cycles 1 (tlsz = 00) 8k x 136-bit 4 2 C 8 (tlsz = 01) 64k x 136-bit 5 9 C 31 (tlsz = 10) 248k x 136-bit 6
41/67 m7010r 136-bit logical search the logical, 136-bit search operation is shown in figure 29. the entire table of 136-bit entries is compared to a 136-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the gmr is the 136-bit word specified by the even and odd global mask pair selected by gmr index in the command s cycle a. the 136-bit word k (present- ed on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs selected by the com- parand register index in the command s cycle b. the two comparand registers can subsequently be used by the learn command with the even- numbered comparand register stored in an even- numbered location, and the odd-numbered com- parand register stored in an adjacent, odd-num- bered location. the word k (presented on the dq busincyclesaandbofthecommand)iscom- pared with each entry in the table starting at loca- tion 0. the first matching entry s location, address l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines. note: the matching address is always going to be an even-numbered address for a 136-bit search. figure 29. x136 table with one device comparand register (even) comparand register (odd) 67 0 a cfg = 01010101 0 2 4 6 16382 (136-bit configuration) location address l b 135 0 ka b gmr even odd 135 0 ai07042 (first matching entry)
m7010r 42/67 272-bit configuration figure 31, page 43 shows the timing diagrams for a search operation in the 272-bit-configured ta- ble (cfg = 10101010) consisting of a single de- vice for one set of parameters: tlsz = 00, hlat = 001, lram = 1, and ldev = 1. the hardware di- agram for this search subsystem is shown in fig- ure 30. C cycle a: the host asic drives the cmdv high and applies the search command code (10) to cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for bits [271:136] of the data being searched. dq[67:0] must be driven with the 68-bit data ([271:204]) to be compared to all locations 0 in the four 68- bits-word page. the cmd[2] signal must be driventologic'1.' note: cmd[2] = 1 signals that the search is a x272-bit search. cmd[8:3] is ignored. C cycle b: the host asic continues to drive cmdv high and continues to apply search command code (10) on cmd[1:0]. the dq[67:0] is driven with 68-bit data ([203:136]) to be compared to all locations 1 in the 68-bits- word page. C cycle c: the host asic drives the cmdv high and applies the search command code (10) to cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for bits [135:0] of the data being searched. cmd[8:6] signals must be driven with the bits that will be driven on sadr[21:19] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) to be compared to all locations 2 in the four 68-bits-word page. the cmd[2] signal must be driven to logic '0.' C cycle d: the host asic continues to drive cmdv high and applies search command code (10) on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and hit flag (see table 9, page 19 for a de- scription of ssr[0:7]). the dq[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations 3 in the four 68-bits-word page. cmd[5:2] is ignored because the learn in- struction is not supported for x272 tables. note: for 272-bit searches, the host asic must supply four distinct 68-bit data words on dq[67:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs that apply to dq data in cycles c and d. the search command is a pipelined operation that executes searches at one-fourth the rate of the frequency of clk2x for 272-bit searches in x272-bit-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 272-bit search command (measured in clk cy- cles) from the clk2x cycle that contains the c and d cycles is shown in table 33, page 44. the timing diagram for all sram interface signals, ssv, and ssf shift to the right for different values of tlsz, as specified in table 31, page 44. in addition, ssv and ssf shift to the right for dif- ferent values of hlat, as specified in table 32, page 44. in the 272-bit configuration, search takes two clk cycles. the result of the search operation appears as an sram read cycle with a pipelined latency measured from the second cycle of the command, as specified in table 33, page 44. figure 30. hardware diagram for a table with one device (272-bit operation) dq[67:0] cmdv, cmd[8:0] ssf, ssv sram lho[1] bhi[2:0] bhi[2:0] lhi 3210 m7010r lho[0] 654 ai07040
43/67 m7010r figure 31. 272-bit configuration search timing diagram (one device) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ale_l, ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l ai04288 a b a b a b a b a b a b a b a b dq d1 d2 1 1 1 11 1 0 0 0 0 0 0 1 0 1 0 0 0 abcd 01 01 hit miss cfg = 10101010, hlat = 001, tlsz = 00, lram = 1, ldev = 1 search1 search2 a1
m7010r 44/67 table 31. right-shift of 272-bit signals for tlsz values table 32. shift of ssf and ssv from sadr (for different hlat values) table 33. latency of search from instruction to sram access cycle (272-bit mode) tlsz number of clk cycles 00 0 01 1 10 2 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 # of devices max table size latency in clk cycles 1 (tlsz = 00) 4k x 272-bit 4 2 C 8 (tlsz = 01) 32k x 272-bit 5 9 C 31 (tlsz = 10) 124k x 272-bit 6
45/67 m7010r 272-bit logical search the logical 272-bit search operation is shown in figure 32. the entire table of 272-bit entries is compared to a 272-bit word k (presented on the dq bus in both cycles a, b, c, and d of the com- mand) using the gmr and the local mask bits. the gmr is the 272-bit word specified by the two pairs of gmrs selected by gmr indexes in the com- mand s cycles a and c. the 272-bit word k (pre- sented on the dq bus in cycles a, b, c, and d of the command) is compared with each entry in the tablestartingatlocation 0. the first matching entry s location, address l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines. note: the matching address is always going to be location 0 in a four-entry page for a 272-bit search (two lsbs of the matching index will be 00 ). figure 32. x272 table with one device cfg = 10101010 0 4 8 12 16380 (272-bit configuration) location address l 271 0 ka b c d gmr 0 1 23 271 0 ai07044 (first matching entry)
m7010r 46/67 mixed-sized searches on tables configured with different width using an m7010r device this subsection will cover mixed searches (x68, x136, and x272) with tables of different widths (x68, x136, and x272). the sample operation shown is for a single device with cfg = 10010000, containing three tables of x68, x136, and x272 widths. the operation can be generalized to a block of 8 to 31 devices using four blocks; the tim- ing and the pipeline operation is the same as de- scribed previously for fixed searches on a table of one-width-size. figure 34, page 47 shows three sequential searches; first, a 68-bit search on a table con- figured as x68, then a 136-bit search on a table configured as x136, and finally a 272-bit search on the table configured as x272. each results in a hit. note: the dq[67:66] will be 00 in each of the two a and b cycles of the x68-bit search (search1). dq[67:66] is 01 in each of the a and b cycles of the x136-bit search (search2). dq[67:66] is 10 in each of the a, b, c, and d cycles of the x272-bit search (search3). by having table des- ignation bits, the m7010r device enables the cre- ation of many tables of different widths in a bank of search engines. figure 33 shows the sample table. two bits in each 68-bit entry need to be designated as table number bits. one example choice might be: the 00 values for the table configured as x68, 01 values for tables configured as x136, and 10 val- ues for tables configured as x272. for the above explanation, it is further assumed that bits for dq[67:66] for each entry will be designed as such table designation bits. figure 33. multiwidth configuration example cfg = 10010000 1k 2k 8k 68 272 136 ai07046
47/67 m7010r figure 34. timing diagram for mixed search (one device) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ale_l, ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l cmd[2] ai07045 a b a b a b a b a b a b a b c d dq d1 d2 d3 a1 a2 1 1 11 1 1 11 0 0 0 0 0 0 0 1 1 00 0 0 a3 01 01 01 search2 x136 hit search3 x272 hit search1 x68 hit cfg = 10101010, hlat = 010, tlsz = 00, lram = 1, ldev = 1 search1 search2 search3
m7010r 48/67 lram and ldev description when search engines are cascaded using multiple m7010r devices, the sadr, ce_l, and we_l (tri-state signals) are all tied together. to eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. for non- search or non-learn cycles (see learn command, page 48) or search cycles with a global miss, the sadr, ce_l, and we_l signals are driven by the device with the lram bit set. it is important that only one device in a bank of cas- caded search engines have this bit set. failure to do so will cause contention on sadr, ce_l, and we_l, and can potentially cause damage to the device(s). similarly, when search engines using multiple m7010r devices are cascaded, ssf and ssv (al- so tri-state signals) are tied together. to eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. for non- search or search cycles with a global miss, the ssf and ssv signals are driven by the device with the lram bit set. it is important that only one device in a bank of cascaded search engines have this bit set. failure to do so will cause contention on ssf and ssv, and can potentially cause dam- age to the device(s). learn command bit [0] of each 68-bit data location specifies wheth- er an entry in the database is occupied. if all the entries in a device are occupied, the device as- serts fulo signal to inform the downstream de- vices that it is full. the result of this communication between depth- cascaded devices determines the global full signal for the entire table. on a miss by the search (signalled to the asic through the ssv and ssf signals [ssv = 1, ssf = 0]), the host asic can apply the learn command to learn the entry from a comparand register to the next-free location (see the nfa register, page 24). the nfa updates to the next-free location following each write or learn command. in a depth-cascaded table, only a single device will learn the entry through the application of a learn instruction. the determination of the learn de- vice is based on the fuli and fulo signalling be- tween the devices. the first non-full device learns the entry by storing the contents of the specified comparand registers to the location(s) pointed to by the nfa. in a x68-configured table, the learn command writes a single 68-bit location. in a 136-bit-config- ured table, the learn command writes the next even and odd 68-bit locations. in 136-bit mode, bit[0] of the even and odd 68-bit locations is '0,' in- dicating that they are cascaded empty, or '1,' which indicates that they are occupied. the global full signal indicates to the table con- troller (the host asic) that all entries within a block are occupied and that no more entries can be learned. the m7010r device updates the signal to a data array after each write or learn com- mand. also using the nfa register as part of the sram address, the learn command generates a write cycle to the external sram. the learn command is supported on a single block containing up to eight devices if the table is configured as either a x68 or a x136. the learn command is not supported for x272-configured ta- bles. the learn operation lasts two clk cycles. the sequence of this operation is as follows: C cycle 1a: the host asic applies the learn instructiononcmd[1:0]usingcmdv=1.the cmd[5:2] field specifies the index of the com- parand register pair that will be written to the data array in the 136-bit-configured table. for a learn in a 68-bit-configured table, the even- numbered comparand specified by this index will be written. cmd[8:6] carries the bits that will be driven on sadr[21:19] in the sram write cycle. C cycle 1b: the host asic continues to drive cmdv to '1,' cmd[1:0] to '11,' and cmd[5:2] with the comparand pair index. cmd[6] must be set to '0' if the learn is being performed on a 68-bit-configured table, and to '1' if the learn is being performed on a 136-bit-configured ta- ble. C cycle 2: the host asic drives cmdv to '0.' at the end of cycle 2, a new instruction can begin. sram write latency is the same as the search to the sram read cycle measured from the second cycle of the learn instruction.
49/67 m7010r learn is a pipelined operation and last for two clk cycles where tlsz = 00, as shown in figure 35, page 49, and tlsz = 01, as shown in figure 36, page 50 and figure 37, page 51. figure 36 and figure 37 assume that the device performing the learn operation is not the last device in the table and has its lram bit set to '0.' note: the oe_l for the device with the lram bit set goes high for two cycles for each learn (one during the sram write cycle, and one during the cycle before it). the latency of the sram write cycle from the second cycle of the instruc- tion is shown in table 34, page 51. figure 35. learn command timing diagram (tlsz = 00) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ale_l, ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l ai04289 a bx x xx xx dq a1 1 1 11 1 1 0 0 0 0 0 1 0 0 0 a2 learn1 learn2 x x tlsz = 00, lram = 1, ldev = 1 comp1 comp2 1a 1b
m7010r 50/67 figure 36. learn timing diagram (tlsz = 1, except on last device) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ale_l, ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l ai07043 a bx x xx xx dq a1 z z z zz z z z 0 0 0 0 z z z = tri-state condition a2 learn1 learn2 x x tlsz = 00, lram = 0, ldev = 0 comp1 comp2 1a 1b
51/67 m7010r figure 37. learn timing diagram on device number 7 (tlsz = 01) table 34. sram write cycle latency from second cycle of learn instruction number of devices latency in clk cycles 1 (tlsz = 00) 4 1-8 (tlsz = 01) 5 1-31 (tlsz = 10) 6 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ale_l, ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l ai07047 a bx x xx xx dq 1 1 11 1 1 0 z z z z z z 1 0 0 0 learn1 learn2 x x tlsz = 01, lram = 1, ldev = 1 comp1 comp2 1a 1b
m7010r 52/67 depth-cascading the search engine application can depth-cas- cade the device to various table sizes in 68-bit, 136-bit, and 272-bit configurations by program- ming the table size (tlsz) field of the command register. the devices perform all the necessary arbitration to decide which device drives the sram bus. the latency of the searches increases as the table size increases while the search rate remains constant. depth-cascading up to eight devices (one block) figure 38, page 53 shows how up to eight devices can cascade to form a 128k x68-bit, 64k x136-bit, or 32k x272-bit table. it also shows the intercon- nection between the devices for depth-cascading. the host asic must program the table size (tlsz) field to '01.' each search engine asserts the lho[1] and lho[0] signals to inform downstream devices in the cascade of its results. the lhi[6:0] signals for any device are connected to the lho signals of the upstream device. a single device alone drives the sram bus in any given cycle. depth-cascading up to 31 devices (4 blocks) figure 39, page 54 shows how to cascade up to four blocks. each block contains up to eight m7010rs (except the last block, which contains 7 devices), to form a 496k x68, 248k x136, or 124k x272 table. note the interconnection between blocks for depth-cascading. the host asic must program the table size (tlsz) field to 10 for cas- cading 8 to 31 devices (in up to four blocks). for each search, a block asserts bho[2], bho[1], and bho[0].the bho[2:0] signals for a block are only taken from the last device in the block. see figure 41, page 56 for the arbitration cycle between blocks to determine which device drives the sram bus. the device is configured to be the last in the depth-cascaded table by setting ldev to 1 in the command register. the device with ldev set to 1 drives the ssf and ssv signals in cycles when all upstream devices do not drive these signals. the m7010r with its ldev bit set drives ssf and ssv during a search with a miss or with non- search commands. see the ldev bit definition in table 10, page 20. depth-cascading to generate a full state for a block bit[0] of each of the 68-bit entries is designated as a special bit (1 = full; 0 = empty). for each learn or pio write to the data array, each de- vice asserts fulo[1] and fulo[0] if it does not have any empty locations (see figure 40, page 55). each device combines the fulo signals from the devices above it with its own full status to gen- erate a full signal, which will then give a full status of the table up to the device asserting the full signal. figure 40, page 55 shows the hard- ware connection diagram for generating the full signal that goes back to the asic. in a depth-cas- caded block of up to eight devices, the full sig- nal from the last device should be fed back to the asic controller to indicate the fullness of the table. the full signal of the other devices should be left open. note: the learn instruction is supported for up to eight devices, whereas full cascading is al- lowed for one block in tables containing more than eight devices. in tables for which a learn instruc- tion will not be used, the bit[0] of each 68-bit entry shouldalwaysbesetto'1.'
53/67 m7010r figure 38. depth-cascading to form a single block (8 devices) dq[67:0] cmdv cmd[8:0] ssf, ssv sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 3210 3210 3210 3210 m7010r m7010r m7010r m7010r m7010r m7010r m7010r m7010r lho[0] 654 654 654 654 654 654 654 654 ai04243
m7010r 54/67 figure 39. four blocks (31 devices cascaded) search, 68-bit configured with ldev = 1 sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block #0 (devices 0 to 7) block of 8 m7010rs block #1 (devices 8-15) block of 8 m7010rs block #2 (devices 16-23) block of 8 m7010rs block #3 (devices 24-30) block of 7 m7010rs ai04242 gnd gnd gnd dq[67:0] cmd[8:0] cmdv ssf, ssv
55/67 m7010r figure 40. full state generation in a cascaded table dq[67:0] fulo[1] fulo[0] fulo[0] fulo[1] fulo[0] fulo[0] fulo[0] fulo[0] fulo[0] fulo[1] fulo[1] fulo[1] fuli fuli fuli fuli fuli fuli fuli fuli fuli fuli fuli 3210 3210 3210 3210 3210 3210 3210 3210 m7010r m7010r m7010r m7010r m7010r m7010r m7010r m7010r fulo[0] 654 654 654 654 654 654 654 654 ai04241 full full full full full full full full v ddq v ddq v ddq v ddq v ddq v ddq v ddq
m7010r 56/67 arbitration figure 41, page 56 shows an example of the arbi- tration cycle for determining which device drives the sram bus in a single block, up to eight m7010rs with 136-bit configuration settings. four cycles from the search command, all m7010rs are informed of the search result within the device and drive their lho signals. at the next cycle, all downstream devices know the outcome of the search in all the upstream devic- es. if any of the upstream devices has a hit, all the subsequent devices defer driving the sram bus. if a search failure occurs, the m7010r with the lram bit set (the last in the chain) drives the sram bus signals. the device with ldev set to '1' is the default driver of the ssv and ssf sig- nals. figure 42, page 57 shows how an m7010r arbitrates accesses to the sram. figure 41. timing diagram for arbitration within a block cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ale_l, ce_l we_l oe_l sadr[21:0] cmd[8:2] phs_ l ai04293 a b dq a1 a2 tlsz = 00, lram = 0, ldev = 0 learn1 learn2 comp1 1a 1b comp2 x x x x x x x x
57/67 m7010r figure 42. timing for arbitration for two or more blocks for the last device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cm d ce_l we_l oe_l sadr[21:0] ssv bho lho ssf cmd[8:2] phs_ l ai04294 a b dq a1 a2 a3 a4 hit hit arbitration cycle within blocks hit miss tlsz = 10, hlat = 000, lram = 1, ldev = 1 search1 search2 search3 3fffff 3fffff search4 d0 d1 d0 d1 d0 d1 d0 d1
m7010r 58/67 sram addressing table 35, page 61 lists and describes the com- mands used to generate addresses on the sram address bus. the index[13:0] field contains the ad- dress of a 68-bit entry that results in a hit in 68-bit configured quadrant. it is the address of the 68-bit entry that lies at the 136-bit page and 272-bit page boundaries in 136-bit and 272-bit configured quadrants, respectively. the register section of this specification describes the nfa and ssr registers. adr[13:0] contains the address supplied on the dq bus during pio ac- cess to the m7010r. command bits 8 and 7, cmd[8:6] are passed from the command to the sram address bus. see command codes and parameters, page 27 for more informa- tion. sram pio access sram read. enables read access to the off- chip sram that contains associative data. the la- tency from the issuance of the read instruction to the address appearing on the sram bus is the same as the latency of the search instruction, and will depend on the value programmed for the tlsz parameter in the device configuration regis- ter. the latency of the ack from the read in- struction is the same as the latency of the search instruction to the sram address plus the hlat programmed into the configuration reg- ister. note: sram read is a blocking operation - no new instruction can begin until the ack is returned by the selected device performing the access. the following explains the sram read operation in a table with only one device and having the fol- lowing parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 43, page 59 shows the associated timing diagram. for the fol- lowing description, the selected device refers only to the device in the table because it is the only de- vice to be accessed. C cycle 1a: the host asic applies the read in- struction on cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[21:19] on cmd[8:6]. C cycle 1b: the host asic continues to apply the read instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram ad- dress. C cycle 2: the host asic floats dq[67:0] to a tri- state condition. C cycle 3: the host asic keeps dq[67:0] in a tri- state condition. C cycle 4: theselecteddevicestartstodrive dq[67:0] and drives ack from high-z to low. C cycle 5: the selected device drives the read address on sadr[21:0]; it also drives ack high, ce_l low, and ale_l low. C cycle 6: the selected device drives ce_l high, ale_l high, the sadr bus and dq bus in a tri-state condition, and ack low. at the end of cycle 6, the selected device floats ack in a tri-state condition, and a new command can begin. table 36, page 62 shows by how many cycles sram signals shift to the right for various tlsz values. table 37, page 62 shows by how many cycles sram signals shift to the right for various hlat values.
59/67 m7010r figure 43. sram read access for one m7010r device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack dq oe_l phs_ l ai04295 read address cmd[8:2] a b ad dress z z 0 0 0 0 1 1 0 z 0 1 1 z we_l sadr ale_l, ce_l ssv ssf dq driven by m7010r tlsz = 00, hlat = 000, lram = 1, ldev = 1
m7010r 60/67 sram write. enables write access to the off- chip sram containing associative data. the laten- cy from the second cycle of the write instruction to the address appearing on the sram bus is the same as the latency of the search instruction, and will depend on the tlsz value parameter pro- grammed into the device configuration register. note: sram write is a pipelined operation - new instruction can begin right after the previous com- mand has ended. the following explains the sram write operation accomplished through a table of only one device with the following param- eters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 44, page 61 shows the timing di- agram. for the following description, the selected device refers to the only device in the table as this is the only device that will be accessed. C cycle 1a: the host asic applies the write in- struction on cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[21:19] on cmd[8:6] in this cycle. note: cmd[2] must be set to '0' for sram write, because burst writes into the sram are not supported. C cycle 1b: the host asic continues to apply the writeinstructiononcmd[1:0]usingcmdv= 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram ad- dress. note: cmd[2] must be set to '0' for sram write, because burst writes into the sram are not supported. C cycle 2: the host asic continues to drive dq[67:0]. the data in this cycle is not used by the m7010r. C cycle 3: the host asic continues to drive dq[67:0]. the data in this cycle is not used by the m7010r. at the end of cycle 3, a new command can begin. the write is a pipelined operation; however, the write cycle appears at the sram bus with the same latency as the search instruction (as mea- sured from the second cycle of the write com- mand).
61/67 m7010r figure 44. sram write access for one m7010r device table 35. sram bus address generation command sram operation 21 20 19 [18:15] [14:0] search read c8 c7 c6 id[4:0] index[14:0] learn write c8 c7 c6 id[4:0] nfa[14:0] pio read read c8 c7 c6 id[4:0] adr[14:0] pio write write c8 c7 c6 id[4:0] adr[14:0] indirect access write/read c8 c7 c6 id[4:0] ssr[14:0] cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack dq oe_l phs_ l ai04296 write address cmd[8:2] a b ad dress x x 1 z 0 0 0 0 0 1 1 we_l sadr ale_l, ce_l ssv ssf tlsz = 00, hlat = 000, lram = 1, ldev = 1
m7010r 62/67 table 36. right-shift of sram signals for tlsz values table 37. right-shift of sram signals for hlat values jtag (1149.1) testing the m7010r supports the test access port (tap) and boundary scan architecture as specified in the ieee jtag standard 1149.1. the pin interface to the chip consists of five signals with the stan- dard definitions: tck, tms, tdi, tdo, and trst_l. table 38, page 62 describes the opera- tions that the test access port controller supports. table 39 shows the tap device id register. note: to disable jtag functionality, connect the tck, tms, and tdi pins to v ddq through a pull- up, and the trst_l to ground through a pull- down. table 38. test access port controller instructions table 39. tap device id register tlsz number of clk cycles 00 0 01 1 10 2 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 instruction type description sample/preload mandatory sample/preload. loads the values of signals going to and from io pins into the boundary scan shift register to provide a snapshot of the normal functional operation. extest mandatory external test. uses boundary scan values shifted in from tap to test connectivity external to the device. intest optional internal test. allows slow-speed, functional testing of the device using the boundary scan register to provide the i/o values. field range initial value description revision [31:28] 0001 revision number. this is the current device revision number. numbers start from one and increment by one for each revision of the device. part # [27:12] 0000 0000 0000 0001 this is the part number for this device. mfid [11:1] 000_1101_1100 manufacturer id. this field is the same as the manufacturer id used in the tap controller. lsb [0:0] 1 least significant bit
63/67 m7010r power distribution guideline in order to prevent voltage supply sags that can potentially degrade device performance, large by- pass capacitors are often recommended. since the bulk storage not only contains an effective se- ries resistance, but also a fairly high inductance, the large bypass capacitors should be assisted by other capacitors that have a lower inductance (but typically less capacitance). these high frequency capacitors control the switching transients and hold-over the power planes during an average load change until the higher inductance capacitors can react. high frequency bypass capacitors are used having values of 0.01uf and 0.1uf. for a single search engine application, a recom- mended power plane and ground plane may be laid out as follows: C a 1000uf bulk capacitor is recommended for the 1.8v v dd source supply. C a 100uf bulk capacitor is recommended for the 3.3v v ddq source supply. C four sets of 0.1uf and 0.01uf high frequency capacitors are recommended between v dd , v ddq and ground. multiple bulk and high frequency capacitors may also be required. users can determine the values of such capacitors after computing, based on their system and power supply environment. the de- vice should achieve the search performance as specified with the bypass capacitors. this application note is a general guideline for search engine design. for more detailed informa- tion, please refer to intel website for appnote ap- 912, pentium iii xeon processor power distribu- tion guidelines. (http://support.intel.com/design/ pentiumiii/xeon/applnots/245095.htm). figure 45. network search engine power distribution ai04297 gnd v ddq v ddq v dd v dd v ddq source v ddq source 100f 1000f 0.1f 0.01f 0.01f 0.1f 0.01f 0.01f 0.1f 0.1f
m7010r 64/67 part numbering table 40. ordering information scheme note: 1. where z is the symbol for bga packages and a denotes 1.27mm ball pitch for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m70 10 r C 083 za 1 t device type m70 search engine density 10 = 1mb (16k x 68-bit table entries) operating supply voltage r=v dd =1.8v speed C 083 = 83 million searches per second C 066 = 66 million searches per second package za = pbga, 272-count, 27mm x 27mm (1) temperature range 1 = 0 to 70 c shipping optio n tape & reel packing = t
65/67 m7010r package mechanical information figure 46. pbga-z00 C 272-ball plastic ball grid array package outline note: drawing is not to scale. table 41. pbga-z00 C 272-ball plastic ball grid array package mechanical data note: 1. maximum mounted height is 2.45mm based on a 0.65mm ball pad diameter. solder paste is 0.15mm thickness and 0.65mm in di- ameter. 2. the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink, or metallized markings, or other feature of package body or integral heatslug. 3. a distinguished feature is allowable on the bottom surface of the package to identify the terminal a1 corner. 4. exact shape of each corner is optional. symb mm inches typ min max typ min max a (4) 27.00 26.80 27.20 (1) 1.102 1.094 1.110 (1) a1 (2,3) 0.60 0.50 0.70 0.024 0.020 0.029 a2 1.63 1.90 0.067 0.078 b (4) 27.00 26.80 27.20 1.102 1.094 1.110 b 0.75 0.60 0.90 0.031 0.024 0.037 d 27.00 26.80 27.20 1.102 1.094 1.110 d1 24.13 0.985 d2 24.00 0.980 e 27.00 26.80 27.20 1.102 1.094 1.110 e1 24.13 0.985 e2 24.00 0.980 e 1.27 0.052 ddd 0.20 0.008 a2 a1 1.17 ref. 0.56 ref. e2 pin #1 d2 ddd c 0.220 (3x) c b a e e e e1 b d1 d 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y 0.300 c 0.100 c s a b s pbga-z00 4.00*45? (4x) 30? typ. b (272x)
m7010r 66/67 revision history table 42. document revision history date rev. # revision details january 2002 1.0 first issue 07/23/02 1.1 changes after extensive review (figures 3, 8, 11, 12, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 43, 44; tables 6, 7, 9, 10, 12, 17, 19, 22, 26, 27, 29, 30, 32, 33, 34, 35)
67/67 m7010r information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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